2021-12-21 20:18:17 +00:00
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from csdr.chain.demodulator import BaseDemodulatorChain, FixedIfSampleRateChain, FixedAudioRateChain, MetaProvider
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2021-09-20 13:32:26 +00:00
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from csdr.module.m17 import M17Module
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2021-12-21 20:18:17 +00:00
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from pycsdr.modules import FmDemod, Limit, Convert, Writer
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2021-09-07 12:45:52 +00:00
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from pycsdr.types import Format
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from digiham.modules import DcBlock
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2021-12-21 20:18:17 +00:00
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class M17(BaseDemodulatorChain, FixedIfSampleRateChain, FixedAudioRateChain, MetaProvider):
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2021-09-07 12:45:52 +00:00
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def __init__(self):
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2021-12-21 20:18:17 +00:00
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self.module = M17Module()
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2021-09-07 12:45:52 +00:00
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workers = [
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FmDemod(),
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DcBlock(),
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Limit(),
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Convert(Format.FLOAT, Format.SHORT),
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2021-12-21 20:18:17 +00:00
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self.module,
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2021-09-07 12:45:52 +00:00
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]
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super().__init__(workers)
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def getFixedIfSampleRate(self) -> int:
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return 48000
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def getFixedAudioRate(self) -> int:
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return 8000
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def supportsSquelch(self) -> bool:
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return False
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2021-12-21 20:18:17 +00:00
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def setMetaWriter(self, writer: Writer) -> None:
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self.module.setMetaWriter(writer)
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