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freedv agc fine-tuning

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This commit is contained in:
Jakob Ketterl 2020-08-29 21:32:21 +02:00
parent 02b4822be8
commit d609acc6aa
1 changed files with 1 additions and 1 deletions
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2
csdr/csdr.py
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@ -246,7 +246,7 @@ class dsp(object):
"csdr agc_ff", "csdr agc_ff",
"csdr convert_f_s16", "csdr convert_f_s16",
"freedv_rx 1600 - -", "freedv_rx 1600 - -",
"csdr agc_s16", "csdr agc_s16 --max 30 --initial 3",
"sox -t raw -r 8000 -e signed-integer -b 16 -c 1 --buffer 32 - -t raw -r {output_rate} -e signed-integer -b 16 -c 1 - ", "sox -t raw -r 8000 -e signed-integer -b 16 -c 1 --buffer 32 - -t raw -r {output_rate} -e signed-integer -b 16 -c 1 - ",
] ]
elif which == "ssb": elif which == "ssb":